Two counters count the clock cycles between the reference levels and the signal and reset levels, then the final value is calculated as the ratio between the two counters.
CMOSIS 2nd Patent on Ramp ADC Granted
CMOSIS announces that its second patent on ramp ADC has been granted. The US8040269 patent proposes to speedup column-level ADC converter by using just one ramp cycle to measure previously sampled column reset and signal levels:
Two counters count the clock cycles between the reference levels and the signal and reset levels, then the final value is calculated as the ratio between the two counters.
Two counters count the clock cycles between the reference levels and the signal and reset levels, then the final value is calculated as the ratio between the two counters.